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Freescale Semiconductor /MK70F12 /MCG /C11

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Interpret as C11

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7 43 0 0 00 0 0 0 0 0 0 0 0PRDIV1 0 (0)PLLCS 0 (0)PLLSTEN1 0 (0)PLLCLKEN1 0 (0)PLLREFSEL1

PLLREFSEL1=0, PLLCLKEN1=0, PLLSTEN1=0, PLLCS=0

Description

MCG Control 11 Register

Fields

PRDIV1

PLL1 External Reference Divider
PLLCS

PLL Clock Select

0 (0): PLL0 output clock is selected.

1 (1): PLL1 output clock is selected.
PLLSTEN1

PLL1 Stop Enable

0 (0): PLL1 clocks (MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X) are disabled in any of the Stop modes.

1 (1): PLL1 and its clocks (MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X) are enabled if system is in Normal Stop mode.
PLLCLKEN1

PLL1 Clock Enable

0 (0): MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are inactive

1 (1): MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are active unless MCG is in a bypass mode with LP=1 (BLPI or BLPE).
PLLREFSEL1

PLL1 External Reference Select

0 (0): Selects OSC0 clock source as its external reference clock.

1 (1): Selects OSC1 clock source as its external reference clock.

Links

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Register License

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data